An Improved Floating Point Addition Algorithm
نویسنده
چکیده
Floating point addition/subtraction has been designed in literature. The methods involved two’s complements add/subtract logic and XOR for counting leading zeroes. This paper proposes algorithm to perform add/subtract operation using one’s complement and counting leading zeroes for normalization using NOR operation as reduction operator for two bits of mantissa at a time. The proposed model is simulated with Quartus 2 version with Cyclone II family processor. An improvement in area by 34% with increased performance of 47% with comparable power consumption is observed when compared with two’s complement add/subtract, XOR operation for leading zeroes count.
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